1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, for example, for a CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor) including a metal gate electrode and a high-k insulation film (high permittivity insulation film).
2. Background Art
Due to a miniaturization of an LSI (Large Scale Integrated circuit), a gate insulation film is required to be thinner than ever. In a CMOS of a 32 nm or smaller node, the gate insulation film is required to have a performance of 0.9 nm or smaller thickness in equivalent oxide thickness. However, in a polysilicon electrode that has been conventionally used as a gate electrode, depletion is caused in the electrode due to its semiconductor characteristics. This increases the effective thickness of the gate insulation film by approximately 0.3 nm, and hinders a reduction of the thickness of the gate insulation film.
To prevent depletion in the gate electrode, there is a demand for an introduction of a metal gate electrode. The metal gate electrode is required to have an effective work function (EWF) near an Si band edge, to reduce the threshold voltage (Vth) of a transistor. More specifically, an NMOSFET (N-channel MOSFET) is required to have an EWF near the Si conduction band edge (4.05 eV), and a PMOSFET (P-channel MOSFET) is required to have an EWF near the Si valence band edge (5.17 eV). By giving the EWF near the Si band edge to the metal gate electrode, the threshold voltage Vth can be lowered, and the CMOS having a desired driving force can be obtained.
Metal nitride is widely considered today as a candidate for a metal gate electrode material, since the metal nitride is thermally stable and is easily etched to form a gate. However, the metal nitride is known to have an EWF near the midgap (approximately 4.6 eV) of the Si bandgap, so that the threshold voltage Vth cannot be reduced simply by employing the metal nitride.
Therefore, where the metal nitride is employed, the threshold voltage Vth is reduced by using an La2O3 (lanthanum oxide) film in the NMOS, or an SiGe (silicon germanium) layer and an Al2O3 (aluminum oxide) film in the PMOS (see JP-A 2007-283208 (KOKAI), for example). In such a case, the La2O3 film is formed between the Si substrate and the metal nitride, to cause an approximately 0.5 eV decrease in the EFW. Also, the SiGe layer is formed in the channel region, and the Al2O3 film is formed between the Si substrate and the metal nitride, to cause an approximately 0.5 eV increase in the EWF. Accordingly, the threshold voltage Vth can be reduced by combining this technique and the metal nitride electrode.
However, when the metal nitride electrode is actually formed on a high-k insulation film, the EWF of the metal nitride electrode becomes approximately 0.2 eV lower than the midgap, due to the high temperature heating processes performed during the manufacture. In such a case, even if the channel SiGe layer and the Al2O3 film are used in the PMOS, an EWF near the Si valence band edge cannot be obtained, and a desired decrease of the threshold voltage Vth cannot be achieved.
Each of JP-A 2007-88122 (KOKAI) and JP-A 2007-243009 (KOKAI) discloses an example of a transistor having a high-k insulation film and a metal gate electrode. More specifically, JP-A 2007-88122 (KOKAI) discloses a p-channel field effect transistor including a high-k insulation film containing hafnium or zirconium, and a titanium nitride film. JP-A 2007-243009 (KOKAI) discloses a p-channel MISFET including a hafnium oxide film, an aluminum oxide film, and a titanium nitride film.